This invention relates to semiconductor devices, for example rectifier diodes, MOSFETs (insulated-gate field-effect transistors), bipolar transistors, IGBTs (insulated-gate bipolar transistors) and thyristors, each having a p-n junction which terminates at a major surface of a semiconductor body and which may be operated under high reverse bias (for example in excess of 200 volts) in at least one mode of operation of the device.
U.S. Pat. No. 4,707,719 (our reference PHB 33126) discloses a semiconductor device comprising a semiconductor body having a body portion of one conductivity type adjacent a major surface of the body, a device region of the opposite conductivity type adjacent said major surface and forming with the body portion a reverse-biased p-n junction which terminates at said major surface, the body portion extending from the device region to an outer periphery of the body portion, and an annular channel stopper extending around the vicinity of the outer periphery. The annular channel stopper disclosed in U.S. Pat. No. 4,707,719 consists of a single doped stopper region 14 of the one conductivity type which is present in the body portion 12 adjacent the upper major surface of the body 10 and which has a higher conductivity type determining doping concentration than the body portion 12. The whole contents of U.S. Pat. No. 4,707,719 are hereby incorporated herein as reference material.
As described in U.S. Pat. No. 4,707,719 the basic device structure may be used for various types of semiconductor device, for example a power rectifier diode, a MOSFET, a bipolar transistor, or a thyristor. The p-n junction 20 is reverse-biased to block voltage in the "off" state of the device. In order to terminate at said major surface, the p-n junction 20 bends towards the surface, so increasing the electric field and reducing the voltage that the device can withstand as compared with that obtainable from a plane (unbent) p-n junction. Some peripheral termination measures are necessary around the bent p-n junction 20 in order to attain the maximum possible blocking voltage when the device is first manufactured (the so-called "zero-hour voltage") and to maintain it during the working life of the device. The blocking voltage is increased by increasing the effective radius of curvature of the p-n junction 20, by an appropriate design of the peripheral termination measures to spread the depletion layer 30 of the p-n junction 20 along the surface of the body portion 12. Ideally, the peripheral termination should be designed to occupy the minimum possible area of the semiconductor body, provide as much of the plane breakdown voltage as possible, be stable over the working life of the device, and cost as little as possible to provide in manufacture.
The peripheral termination measures disclosed in U.S. Pat. No. 4,707,719 include the provision of a resistive overlayer 28 on an insulating layer 18 over the whole semiconductor body surface between the channel stopper region 14 of the one conductivity type and the device region of the opposite conductivity type. This resistive overlayer 28 acts as a field plate to spread the depletion layer from the reverse-biased p-n junction 20 towards the outer periphery. At least one field region 1-6 of the opposite conductivity type is also provided between the annular channel stopper region 14 and the device region 11, surrounds the device region 11 and forms with the body portion 12 of the one conductivity type a p-n junction 21-26 terminating at said major surface. The field regions 1-6 also control the spread of the depletion layer 30 in the body portion.
The resistive overlayer 28 on the insulating layer 18 provides also an effective means for electrically screening the underlying body surface from external changes and for inhibiting the diffusion of contaminating ions into the peripheral termination from, for example, a plastics encapsulation around the semiconductor body 10. In the absence of the measures 18 and 28, these external changes and contaminating ions can undesirably alter the internal fields in the peripheral termination area, so changing the blocking voltage characteristics of the device during its working life. The peripheral termination measures (1-6,14,18,28) disclosed in U.S. Pat. No. 4,707,719 are particularly effective, because they screen the whole body surface from the device region to the outer periphery and because the potential variation along the semiconductor body surface is matched to that in the resistive overlayer. However, these measures may occupy quite a large peripheral area of the semiconductor body. Furthermore, there is a leakage current which flows through the resistive overlayer 28, across the blocking p-n junction 20.
U.S. Pat. No. 4,954,868 discloses an alternative approach in which (instead of a resistive overlayer) discrete field plates are used connected to various regions of the device. The whole contents of U.S. Pat. No. 4,954,868 are hereby incorporated herein as reference material. The annular channel stopper in the device of U.S. Pat. No. 4,954,868 is a field plate 7 rather than a doped region of the semiconductor body 1. The blocking p-n junction 3 of the device is covered by a field electrode 6. The blocking voltage is increased by arranging a further channel-stopper field plate 19 over the channel stopper 7 and an anode field plate 18 over the field electrode 6. These field plates 18 and 19 extend towards each other on a further insulating layer 16. This further insulating layer 16 is not of uniform thickness. The thickness of the insulating layer 16 is larger between the field plates 18 and 19 than it is over the field electrode 6 and channel stopper 7.
A gap c is present between the field plates 18 and 19 of the device of U.S. Pat. No. 4,954,868. The increased dielectric thickness for the insulating layer 16 around the gap c reduces capacitive coupling between charges at the top surface of the dielectric and the underlying major surface of the semiconductor body. The gap c is advantageous in that it inhibits leakage current across the blocking junction 3, through the field plates 18 and 19. However, the requirement for such a gap c prevents the peripheral termination measures from covering the whole of the semiconductor body surface from the blocking p-n junction 3 to the channel stopper 7. Furthermore, the need to provide a further dielectric layer 16 of differing thickness below the field plates 18 and 19 can be inconvenient in manufacture, and the control of the increased thickness for this dielectric layer 16 may become a critical process parameter.